- Updated Joystick Support, by @Flandango
- Some simple reworking
- Solved MDA resolution by adding videomixer instance and 113.75 pll clock, and other minor code changes, by @somhi
- Fix BIU (Now, PKUNZIP works), by @kitune-san and @MicroCoreLabs
- Solved left overscan column in CGA mode, by @somhi
New arcade core: Irem M72
- R-Type, Ninja Spirit, Image Fight, Gallop - Armed Police Unit, Legend of Hero Tonma, Mr. HELI no Daibouken, Air Duel, Dragon Breed, X Multiply
- Supports pause and screen rotation
- Alternative 50hz, 57hz and 60hz video modes
- Emulated MCU support for cores with missing MCU dumps
- Added Daiku no Gensan (Hammerin' Harry)
- Added sample playback to Gallop
- Adjust timing for audio in sorcer and kingdom (again)
- Adjust all cores and meet all timing constraints
- Swap pll properly to 94.5 mhz for SDRAM compatibility, adjust all clocks and frequencies
- Add 2 build profiles for each core, one for development purposes (fast build) can get you an RBF in 8 mins, but not meet timing constraints 100%, and other is normal production build, which is about 20 mins. You can switch between the profiles in quartus UI.
- Fix 8253 Timer, by @kitune-san
- Scanlines working solved in MDA mode, by @somhi
- Reworking overscan delays to PCXT.sv
- Border feature for CGA/Tandy
- Overscan colour fix in Tandy Mode
New Core: Casio PV-1000
Games affected by fixes:
Spyro 2+3 PAL, OpenBIOS, Red Asphalt USA, Next Tetris, Tom & Jerry PAL, Loaded, FEDA 2, GTA PAL, Gouketuji Ichizoku 2, Suiko Enbu, Battle Arena Toshinden
- always fill turbo data cache -> allows turbo to be switched on/off at runtime
- CPU: implement instruction cache valid bits for every word of a cache line
- CPU: modify stalling to support single cycle data store
- CPU/MEM: add 4 word CPU write queue in data store path
- MEM: 1 cycle faster writing of register busses
- MEM: add save function for memory requests, while module is busy
- MEM: always fill data cache -> allows turbo to be switched on/off at runtime
- MEM: correct timing of ram write in respect to ram page
- MEM: various fixes for bus width and timing accuracy for SPU and EXP1-3
- DMA: rework DMA->SDRAM interface: double write performance, decrease overhead by 4 cycles
- Timer: various accuracy fixes
New Core: Pokemon Mini (Nintendo 2001)
- Improve trackball/mouse support
- Update framework
- 4 x 32Kb pages for Tandy 320x200x16 mode (More Tandy games now working)
- VRAM resizing for MDA to 4Kb
- LPT port mapping fix
- Removed DSS/Covox support (Not feasible for this core)
- Renamed option 'Zoom', to '240p Mode' for clarity.
- Renamed 'Shock' button to 'Shock Sensor'.
- Fixed implementation of 2 instructions, affecting at least 2 commercial games.
- Fixed a problem where pushing the power button results in reboot instead of shutdown.
- Handling of the border colour register in Tandy
- Handling of the NMI register for video memory paging (more compatible games, such as Another World and Ski or Die)
- Override build_id.tcl script to automatically inject build date in cfgstr.
- Fix mapping of fx level option (high=100%, very high = 200%, very low = 50%, low = 75%)
- Adjust default fm level of batrider to 50%.
- (Hopefully) fix issue with scroll layers disappearing when free play dip is set in bakraid
- Fixed sound cracking/popping. This was mostly prominent in the bad apple demo.
- Fixed blitter timing issues. At least one game was known to be affected by this (Pokemon Party mini).
- Reduced overall sound level to be more in line with other console cores.
- GSU & PPU fixes (srg320).
- SNAC auto detect, organize OSD input options (blue212).
- Framework update.
- Support for R-Type 2, M84 hardware
- Added 240p crop option
- Added Analog video h/v adjustments
- Re-organized OSD
New Arcade Core: Inferno
- Original core developed by darfpga now ported to MiSTer by JasonA and birdybro
- Sound effects don't all play correctly, this is already known.
* Gave joystick analog inputs precedence over digital (d-pad) inputs if both were triggered at the same time. This resolves default mapping issues some users were having if they had not defined gamepad inputs inside the core.
- Sound from PIA 6821 chip fixed thanks to @darfpga
- Modified fitter settings slightly to meet timing requirements more reliably.
Fixes and improvements from @gyurco
- Support Hammerin' Harry M84
- M84 sample playback rate fixes
- Reduce sprite bram usage
- fix issue with mirrored sprite seam calculation (ie. batrider intro tank missing 1 pixel at the end due to 2 sprites, 1 mirrored, joined at a seam).
- improve performance of obj engine due to lower clock change to 94.5.
New Arcade Core: Galivan
- Support for Cosmo Police Galivan & UFO Robo Dangar
- Fixed RTC timer being stuck resetting. This affected homebrew demo SHizZLE.
- Fixed bug which can occur after loading a new rom or resetting the core.
- Implemented remaining jump conditions. This fixes a few hombrew games.
- Fix interrupt controller.
- sound: Updated the DSP write port status busy flag (user7182).
- remove the press-to-see need for joystick to prevent configuration issues in games (Kitrinx).
- Add option to disable joysticks.
- Support for steering wheel.
- Updated framework.
- Messages : 128
- Inscription : 02 avr. 2022 - 17:49
- Localisation : Metz / Lux
- A remercié : 2 fois
- A été remercié : 17 fois
- Audio mixer based on that of ao486
- New BIOS loader based on SDRAM, by @kitune-san
- Fix 8288, by @kitune-san
- Fixed tape loading audio OSD option, by @Flandango
- implement 3 different turbo speeds
- Move datacache into CPU -> speedup when using turbo setting "high"
- fixed memory card loading edge case leading to memory card data not being available
- fixed wrong savestate slot index when loading core
- fixed edge case where loading a savestate would hang up the core until reset is triggered
- fixed CPU blockLoadforward edge case (CPU test from pcsx-redux is now pass)
- many cleanups and resource reductions, FPGA logic went from 97% to 93%
- Memory: CD register bus is now using extbus logic
- Memory: extbus timing modified when using PStrobe together with RecP(CD timings)
- Memory: adjust timings for BIOS reads
- Memory: rework sdram -> instruction cache interface, reducing cache fetch time by 1 cycle, fulfilling test against hardware
- CPU: implement out-of-order load pipelining
- CPU: implement readback of CACHECONTROL register
- CPU: make instruction fetch stage fully independent of data fetch stage
- DMA: add timing cost for ram page switch and refresh
- DMA: reduce initial overhead by 2 cycles
- Timer: implement non-retrigger mode by using Mode bit 6